Corresponding to the increased operating frequency and complexity of electronic devices, for example, with high-definition television (HDTV), there is a need for analog-to-digital converters (“ADCs”) to operate at higher sampling rates as well as provide greater conversion resolution. Typically, an ADC that is capable of operating at sufficiently high sampling rates must trade-off conversion resolution, while a high conversion resolution ADC usually is not capable of operating at a high sampling rate.
Delta-sigma modulators generally employ noise-shaping and over-sampling techniques to perform analog-to-digital conversion (“A/D conversion”) at relatively high resolution for signals of modest bandwidth as described in the book by S. R. Norsworthy, R. Schreier, and G. Temes, entitled “Delta-Sigma Data Converters,” IEEE Press, January 1997. The main advantages of such modulators over alternative A/D conversion schemes are the use of analog circuits with precision much less than the resolution of the overall converter, compatibility with advanced nanometer-scaled CMOS technology, and the ability to trade resolution in time for resolution in amplitude by digital decimation and low-pass filtering.
For a given signal bandwidth, design options available to attain high resolution are increasing the modulator order and/or employing multi-bit quantization. Arbitrarily increasing the order of the modulator in single-stage loops may lead to modulator instability. The stability problem can be mitigated by cascading stable lower order stages that operate in cooperation to attain higher order “Multi-stAge noise-SHaping” (“MASH”) noise shaping. On the other hand, utilizing multi-bit quantizers yields approximately a 6 dB improvement in signal-to-noise ratio (SNR) for each additional bit, as described by T. Leslie and B. Singh in the paper entitled “An Improved Sigma-Delta Modulator Architecture,” in the Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 372-375, 1990, which is hereby referenced and incorporated herein. This means increased resolution can be obtained without increasing the over-sampling ratio. Equivalently, a multi-bit modulator can achieve a resolution comparable to that of a similar single-bit modulator at a lower sampling rate. This performance improvement can be a significant advantage in applications requiring wide conversion bandwidth. However, problems persist in implementing multi-bit quantizers beyond a few bits within a delta-sigma loop because they usually must employ a “flash-type” ADC, i.e., they must perform rapid conversion within one clock cycle using arrayed flash type comparators, because conversion latency cannot be tolerated in the delta-sigma loop, which may lead to instability. The limitation of this approach is that complexity must grow exponentially with resolution because flash type component count is proportional to 2N, where N is the number of bits of converter resolution.
Turning now to FIG. 1, illustrated is a block diagram of a delta-sigma modulator 100 of the prior art with an input X(n), representing an analog input signal at cycle n, and an output digital word Y(n) at cycle n. The delta-sigma modulator 100 is typically operated periodically to produce the output sequence Y(n), and can be implemented using digital signal processing techniques. The input signal X(n) and the output of the digital-to-analog converter (a “DAC”) 140 are subtracted in adder 110, and the cycle-to-cycle result is summed in block 120. Block 120, illustrated in the figure with Z-transform notation for a sampled-data system, represents a summing process, i.e., block 120 is an analog “integrator.” Block 120 typically executes the equationL(n+1)=L(n)+U(n),where U(n) and L(n) are, respectively, the input and output of the integrator at cycle n, and L(n+1) is the output of the integrator at cycle n+1. Quantizer 130 reduces the bit width of the output word of the delta-sigma modulator to produce the output sequence Y(n), each word of which may only be a single bit. DAC element 140 executes the equationW(n)=Y(n−1),where W(n) is the output from the DAC element at cycle n, and Y(n−1) is the input to the element at the previous cycle. A DAC element is implemented by converting the input digital word to its equivalent analog representation. The delta-sigma modulator illustrated in FIG. 1 is thus an analog processing circuit that produces a sequence of output words Y(n) that assume values with average value equal to the average value of the input signal X(n).
A second-order delta-sigma modulator of the prior art is illustrated in the block diagram in FIG. 2, including the two integrators 215 and 220. This modulator is referred to as a second-order modulator because it includes two integrators (or “integration stages”). The output word Y(n) in this design may be quantized to a bit width of one, and alternately assume the values +1 and −1 after processing by quantizer 225.
Modulators with higher orders of integration come with increased cost as measured by indicators such as die area, gate count, signal processing delay, and power dissipation. Nonetheless, modulators of higher order, such as the modulator illustrated in FIG. 2, allow the output signal to track the input signal with improved accuracy.
Leslie and Singh describe in the paper previously cited, as illustrated in FIG. 3, a second-order noise-shaping analog-to-digital converter with single-bit feedback in a multi-loop modulator. In this multi-bit quantizing arrangement, only the most significant bit is fed back, thereby requiring only a single bit digital-to-analog converter. The need to calibrate a multi-bit digital-to-analog converter is thereby avoided. Nonetheless, a limitation of Leslie and Singh is that no additional noise-shaping is provided for the m-bit quantization error.
T. Brooks, et al., in the paper entitled, “A 16b Sigma-Delta Pipeline ADC with 2.5 MHz Output Data-Rate,” International Solid State Circuits Conference, February 1997, pp. 208-209, (“Brooks”) which is hereby referenced and incorporated herein, describe an analog-to-digital converter employing delta-sigma modulation using pipelined analog-to-digital conversion techniques with oversampling to achieve rapid signal conversion. The structure of an ADC as described by Brooks employing an internal k-bit flash ADC is illustrated in FIG. 4. Brooks' architecture is limited because it requires complex dynamic element matching (“DEM”) in a k-bit DAC incorporated within the delta-sigma loop.
Recognizing that applications of delta-sigma modulators serve large, competitive markets, many serving portable applications operable from battery power, a low-cost delta-sigma modulator, particularly one that consumes low-power, provides fast and accurate multi-bit conversion of an analog signal into a digital format, would provide a competitive advantage. Thus, what is needed in the art is a delta-sigma modulator that can produce a high-frequency sequence of binary words with high accuracy and minimal signal processing. Further, a need exists for an improved delta-sigma modulator that can advantageously be produced in an integrated circuit with low cost and with fast signal-processing speed, and which has less drain on the battery system for portable devices than devices that are produced with existing technology.